A conventional method of producing both MOS transistors having relatively high drain-junction breakdown voltages, and precision resistors, in an integrated circuit, provides for the use of a single polycrystalline silicon mask and a single implantation step to produce together a weakly doped zone of the drain region and a high-resistivity region for the resistor. As will be explained in greater detail below, this method requires the formation of a silicon dioxide layer on the polycrystalline silicon mask and anisotropic etching of this layer throughout its area to add a masking border to the gate strips before the usual high-dose implantation of the source and drain regions. For this operation to be effective, the etching has to be continued until a thin surface layer has been removed from the uncovered regions of the semiconductor material. The semiconductor material is normally monocrystalline silicon, and which provides the substrate. This causes a depletion of the doping of these regions, and, hence, an increase in their resistivity. This increase in resistivity does not appreciably affect the final characteristics of the transistors, but considerably affects the values of the resistors.
Since, to ensure correct operation of the integrated circuit, the values of the resistors must not differ from the design values, the over-etching may adversely affect the electrical characteristics of the circuit or may render the design more complex since it requires certain compensation circuitry. In any case, apart from the over-etching problem, the known method renders the breakdown voltage of the MOS transistors and the resistances of the precision resistors interdependent. Moreover, in certain cases this provides a considerable limitation on the design of the circuit.
One possible approach to this problem is to use two separate masks and two separate implantation steps to form the MOS transistors with high breakdown voltages and to form the precision resistors. However, this approach complicates the manufacturing process with a consequent increase in the number of defects in the resulting integrated circuits, and, hence, a reduction in production output.